// Cell names have been changed in this file by netl_namemap on Mon Jan  3 04:00:08 UTC 2022
////////////////////////////////////////////////////////////////////////////// 
//
//  pcs_raw_gen_glcm.v
//
//  Glitchless clock mux
//
//  Original Author: Behram Minwalla
//  Current Owner:   Behram Minwalla
//
////////////////////////////////////////////////////////////////////////////// 
//
// Copyright (C) 2009 Synopsys, Inc.  All rights reserved.
//
// SYNOPSYS CONFIDENTIAL - This is an unpublished, proprietary work of
// Synopsys, Inc., and is fully protected under copyright and trade secret
// laws.  You may not view, use, disclose, copy, or distribute this file or
// any information contained herein except pursuant to a valid written
// license agreement. It may not be used, reproduced, or disclosed to others
// except in accordance with the terms and conditions of that agreement.
//
////////////////////////////////////////////////////////////////////////////// 
//
//    Perforce Information
//    $Author: spagnuol $
//    $File: //dwh/up16/main/dev/pcs_raw/dig/rtl/pcs_raw_gen_glcm.v $
//    $DateTime: 2015/10/26 08:06:03 $
//    $Revision: #4 $
//
////////////////////////////////////////////////////////////////////////////// 

module dwc_e12mp_phy_x4_ns_pcs_raw_gen_glcm
#(parameter CLK_A_RST_VAL = 0,
  parameter CLK_B_RST_VAL = 0) (
input  wire clk_sel,
input  wire clk_a,
input  wire clk_b,
input  wire rst_a,
input  wire rst_b,
input  wire scan_mode_i,
input  wire scan_shift_cg_i,
input  wire scan_set_rst_i,
output wire clk_out,
output wire clk_a_en_out,
output wire clk_b_en_out
);

wire s_a2;
wire s_b2;

reg  s_a3;
reg  s_b3;

wire clk_a_en;
wire clk_b_en;

dwc_e12mp_phy_x4_ns_gen_clk_and2 clk_a_en_and (
  .out (clk_a_en), 
  .clk (~s_b3), 
  .en  (~clk_sel)
);

// Register clock enable 3x
// This is a phase path with clk_b.
dwc_e12mp_phy_x4_ns_gen_sync #(.RST_VAL(CLK_A_RST_VAL)) clk_a_sync (
  .q   (s_a2),
  .rst (rst_a),
  .clk (clk_a),
  .d   (clk_a_en)
);

// Mantis 6859 - Add an additional clock cycle on s_a2 to ensure the
// has been completely disabled
always @(posedge clk_a or posedge rst_a) begin
   if (rst_a)
      s_a3 <= CLK_A_RST_VAL;
   else
      s_a3 <= s_a2;
end

dwc_e12mp_phy_x4_ns_gen_clk_and2 clk_b_en_and (
  .out (clk_b_en), 
  .clk (~s_a3), 
  .en  (clk_sel)
);

// Register clock enable 3x
// This is a phase path with clk_a.
dwc_e12mp_phy_x4_ns_gen_sync #(.RST_VAL(CLK_B_RST_VAL)) clk_b_sync (
  .q   (s_b2),
  .rst (rst_b),
  .clk (clk_b),
  .d   (clk_b_en)
);

// Mantis 6859 - Add an additional clock cycle on s_b2 to ensure the
// clock has been completely disabled
always @(posedge clk_b or posedge rst_b) begin
   if (rst_b)
      s_b3 <= CLK_B_RST_VAL;
   else
      s_b3 <= s_b2;
end

wire clk_a_gated;
wire clk_b_gated;
dwc_e12mp_phy_x4_ns_gen_clk_gate clk_a_s_gate (
 .en_clk          (clk_a_gated),
 .clk             (clk_a),
 .rst             (rst_a),
 .en              (s_a2),
 .scan_mode_i     (scan_mode_i),
 .scan_shift_cg_i (scan_shift_cg_i),
 .scan_set_rst_i  (scan_set_rst_i)
);

dwc_e12mp_phy_x4_ns_gen_clk_gate clk_b_s_gate (
 .en_clk          (clk_b_gated),
 .clk             (clk_b),
 .rst             (rst_b),
 .en              (s_b2),
 .scan_mode_i     (scan_mode_i),
 .scan_shift_cg_i (scan_shift_cg_i),
 .scan_set_rst_i  (scan_set_rst_i)
);

// Mantis 6679 - hand instantiate OR gate in GLCM
dwc_e12mp_phy_x4_ns_pcs_raw_gen_clk_or2 clk_a_or_b (
  .out  (clk_out), 
  .clk1 (clk_a_gated), 
  .clk2 (clk_b_gated)
);

// Output the final clock enables.  This is done so the higher
// level can determine if a clock has been enabled
assign clk_a_en_out = s_a3;
assign clk_b_en_out = s_b3;

endmodule

